The application of digital processing systems to problems of control and computation is rapidly expanding. Advances in the integration of systems on chip (SoC) have made possible a wide variety of new industrial and consumer products and capabilities. A prime example is a cellular telephone. These devices typically utilize a digital signal processor (DSP) to encode voice data, which has been acquired by means of an analog to digital converter, into a binary data stream suitable for transmission over a cellular network. The digital signal processor operates on data in a fixed-point representation. The DSP may be a separate integrated circuit, or it may be one component of an SoC, another typically being a microprocessor core providing additional control and features to the telephone.
It is possible to combine the microprocessor and DSP units in varying numbers: For example, in the journal publication entitled “Interfacing Multiple Processors in a System-on-Chip Video Encoder” by Erno Salminen et al., an SoC is described which implements a RISC processor core interfaced with two fixed-point DSP cores.
Although SoCs combining a microprocessor and one or more fixed-point DSP units are useful for a wide variety of applications, they suffer from a number of limitations:
First, the absence of floating-point capability in SoC DSPs limits algorithm development and adaptation for these systems. A variety of useful and well-known algorithms are more easily ported to the DSP using a floating-point number representation. One example is matrix inversion, a key ingredient for numerical analysis. This algorithm, and many others, can be ported in a more direct and simplified manner if the data are represented in floating-point format. The prior art fails to recognize this opportunity. For example, U.S. Pat. No. 6,260,088 B1 to Gove et al. discloses in column 16, lines 4-36 that an SoC combining a RISC processor and a DSP would preferably implement floating-point operations on the RISC processor, and restrict the DSP to fixed-point arithmetic, stating on lines 13-14 “ . . . the low level processors do not require floating-point arithmetic . . . ”
Second, although discrete floating-point DSPs are known in the art, all represent the data with limited precision, typically 32 bits. It is appreciated by those skilled in the art that the allocation of bits to the mantissa and exponent of a floating-point number sets limits to the precision and dynamic range of the data which can be represented. Many desirable applications can require processing of data which exceeds the precision and dynamic range capabilities of a typical 32-bit floating-point representation in which 24 bits are assigned to the mantissa and 8 bits to the exponent. This could, for example, include an analysis and reproduction of a 132 dB (22-bit) transient impulse embedded in a 96 dB (16-bit) signal. A situation of this type may be encountered in a symphonic attack after a crescendo, or in the simulation of a gunshot in a movie, simulation, or video game soundtrack. Diagnosis and analysis of data from noisy environments can also produce this type of situation.
Third, no floating-point DSP known in the art offers dedicated assembler instructions for single cycle computations on complex numbers. Complex-domain computations are frequently encountered in frequency domain algorithms, time-frequency domain analysis, and frequency-spatial wave-number algorithms. The well-known Fast Fourier Transform (FFT) is defined by means of complex algebra, and the capability of complex domain assembler instructions would enable a DSP to provide native support for the FFT, greatly facilitating applications to audio, radio, or ultrasound wave processing. The prior art has concentrated on computation of the FFT using integer number representations for complex numbers. For example, U.S. Pat. No. 6,317,770 to Lim et al. discloses in column 12, lines 50 through 55 that “ . . . in the DSP according to the present invention . . . thereby performing the fixed-point and integer arithmetics in a high speed as well as simplifying the circuit configuration.” It should be appreciated by those skilled in the art that floating-point complex arithmetic is an appropriate granularity for exploitation of instruction level parallelism at both the compiler and silicon levels, and for DSP application kernels.
Overcoming these foregoing limitations in a system with high processing speed would enable improvement or extension of SoC signal processing into applications such as:                1. Hands-free telephones incorporating multi-microphones, echo cancellation, and audio beam forming;        2. Ultrasound image scanners with better diagnostic image quality;        3. Adaptive sound equalization for home, auto, and cinema creating environment specific pre-equalization and pre-reverberation; and        4. Improved hearing aids and ear prostheses based on real time modeling of the cochlea.        
What is needed is a complete signal processing platform which combines floating-point data representation, extended precision and complex domain arithmetic with adaptable control and system interfacing capability.